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for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. general description the max17003/max17004 are dual step-down, switch- mode, power-supply (smps) controllers with synchro- nous rectification, intended for main 5v/3.3v power generation in battery-powered systems. fixed-frequen- cy operation with optimal interleaving minimizes input ripple current from the lowest input voltages up to the 26v maximum input. optimal 40/60 interleaving allows the input voltage to go down to 8.3v before duty-cycle overlap occurs, compared to 180 out-of-phase regula- tors where the duty-cycle overlap occurs when the input drops below 10v. output current sensing provides peak current-limit pro- tection, using either an accurate sense resistor or using lossless inductor dcr current sensing. a low-noise mode maintains high light-load efficiency while keeping the switching frequency out of the audible range. an internal, fixed 5v, 100ma linear regulator powers up the max17003/max17004 and their gate drivers, as well as external keep-alive loads. when the main pwm regu- lator is in regulation, an automatic bootstrap switch bypasses the internal linear regulator, providing current up to 200ma. an additional adjustable linear-regulator driver with an external pnp transistor may be used with a secondary winding to provide a 12v supply, or powered directly from the main outputs to generate low-voltage outputs as low as 1v. independent enable controls and power-good signals allow flexible power sequencing. voltage soft-start grad- ually ramps up the output voltage and reduces inrush current, while soft-discharge gradually decreases the output voltage, preventing negative voltage dips. the max17003/max17004 feature output undervoltage and thermal-fault protection. the max17003 also includes output overvoltage-fault protection. the max17003/max17004 are available in a 32-pin, 5mm x 5mm, thin qfn package. the exposed backside pad improves thermal characteristics for demanding linear keep-alive applications. applications main power supplies 2 to 4 li+ cell battery-powered devices notebook and subnotebook computers pdas and mobile communicators features fixed-frequency, current-mode control 40/60 optimal interleaving internal bst switches internal 5v, 100ma linear regulator auxiliary linear-regulator driver (12v or adjustable down to 1v) dual mode feedback?.3v/5v fixed or adjustable output voltages 200khz/300khz/500khz switching frequency undervoltage and thermal-fault protection overvoltage-fault protection (max17003 only) 6v to 26v input range 2v ?.75% reference output independent enable inputs and power-good outputs soft-start and soft-discharge (voltage ramp) 8? (typ) shutdown current max17003/max17004 high-efficiency, quad-output, main power- supply controllers for notebook computers ________________________________________________________________ maxim integrated products 1 19-0765; rev 0; 3/07 + denotes lead-free package. max17003 max17004 thin qfn 5mm x 5mm top view 29 30 28 27 12 11 13 drva shdn on3 on5 ref 14 ona dl3 in ldo5 lx3 pgnd dl5 12 + csl3 4567 23 24 22 20 19 18 csh3 fb3 dschg5 csl5 csh5 fb5 ilim pgdall 3 21 31 10 fba skip 32 9 outa fsel dschg3 26 15 bst5 bst3 25 16 dh5 gnd lx5 8 17 dh3 pin configuration ordering information part temp range pin- package pkg code max17003 etj+ -40? to +85? 32 thin qfn (5mm x 5mm) t3255-4 max17004 etj+ -40? to +85? 32 thin qfn (5mm x 5mm) t3255-4 dual mode is a trademark of maxim integrated products, inc. evaluation kit available
max17003/max17004 high-efficiency, quad-output, main power- supply controllers for notebook computers 2 _______________________________________________________________________________________ absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. in, shdn , drva, outa to gnd............................-0.3v to +28v ldo5, on3, on5, ona to gnd ..............................-0.3v to +6v pgdall, dschg3, dschg5 to gnd .....................-0.3v to +6v csl3, csh3, csl5, csh5 to gnd ..........................-0.3v to +6v ref, fb3, fb5, fba to gnd...................-0.3v to (v ldo5 + 0.3v) skip , fsel, ilim to gnd........................-0.3v to (v ldo5 + 0.3v) dl3, dl5 to pgnd..................................-0.3v to (v ldo5 + 0.3v) bst3, bst5 to pgnd .............................................-0.3v to +34v bst3 to lx3..............................................................-0.3v to +6v dh3 to lx3 ..............................................-0.3v to (v bst3 + 0.3v) bst5 to lx5..............................................................-0.3v to +6v dh5 to lx5 ..............................................-0.3v to (v bst5 + 0.3v) gnd to pgnd .......................................................-0.3v to +0.3v bst3, bst5 ldo5 .................................................-0.3v to +0.3v ldo short circuit to gnd ..........................................momentary ref short circuit to gnd ...........................................momentary drva current (sinking) ......................................................30ma outa shunt current ...........................................................30ma continuous power dissipation (t a = +70?) multilayer pcb 32-pin, 5mm x 5mm tqfn (derated 34.5mw/? above +70?) .........................2459mw operating temperature range ...........................-40? to +85? junction temperature ......................................................+150? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) ................................+300? electrical characteristics (circuit of figure 1, v in = 12v, both smps enabled, fsel = ref, skip = gnd, ilim = ldo5, fba = ldo5, i ref = i ldo5 = i outa = no load, t a = 0? to +85? , unless otherwise noted. typical values are at t a = +25?.) parameter symbol conditions min typ max units input supplies (note 1) ldo5 in regulation 5.4 26.0 v in input voltage range v in in = ldo5, v csl5 < 4.4v 4.5 5.5 v v in operating supply current i in ldo5 switched over to csl5, either smps on 20 36 ? v in standby supply current i in(stby) v in = 6v to 26v, both smps off, includes i shdn 65 120 ? v in shutdown supply current i in(shdn) v in = 6v to 26v 8 20 a quiescent power consumption p q both s m p s on, fb3 = fb5 = ld o5, skip = gn d , v c s l 3 = 3.5v , v c s l 5 = 5.3v , v ou t a = 15v , p in + p c s l 3 + p c s l 5 + p ou t a 3.5 4.5 mw main smps controllers 3.3v output voltage in fixed mode v out3 v in = 6v to 26v, skip = fb3 = ldo5, 0 < v csh3 - v csl3 < 50mv (note 2) 3.265 3.315 3.365 v 5v output voltage in fixed mode v out5 v in = 6v to 26v, skip = fb5 = ldo5, 0 < v csh5 - v csl5 < 50mv (note 2) 4.94 5.015 5.09 v v in = 6v to 26v, fb3 or fb5 duty factor = 20% to 80% 1.980 2.010 2.040 feedback voltage in adjustable mode (note 2) v fb_ v in = 6v to 26v, fb3 or fb5 duty factor = 50% 1.990 2.010 2.030 v
max17003/max17004 high-efficiency, quad-output, main power- supply controllers for notebook computers _______________________________________________________________________________________ 3 electrical characteristics (continued) (circuit of figure 1, v in = 12v, both smps enabled, fsel = ref, skip = gnd, ilim = ldo5, fba = ldo5, i ref = i ldo5 = i outa = no load, t a = 0? to +85? , unless otherwise noted. typical values are at t a = +25?.) parameter symbol conditions min typ max units output voltage adjust range either smps 2.0 5.5 v fb3, fb5 dual-mode threshold 3.0 v loo5 - 1.0 v loo5 - 0.4 v feedback input leakage current v fb3 = v fb5 = 2.1v -0.1 +0.1 a dc load regulation either smps, skip = ldo5, 0 < v csh_ - v csl < 50mv -0.1 % line regulation error either smps, 6v < v in < 26v 0.03 %/v fsel = gnd 170 200 230 fsel = ref 270 300 330 operating frequency (note 1) f osc fsel = ldo5 425 500 575 khz maximum duty factor d max (note 1) 97.5 99 % minimum on-time t onmin 100 ns 40 % smps3-to-smps5 phase shift smps5 starts after smps3 144 deg current limit ilim adjustment range 0.5 v ref v current-sense input leakage current csh3 = csh5 = gnd or ldo5 -1 +1 ? current-limit threshold (fixed) v limit v csh _ - v csl _, ilim = ldo5 45 50 55 mv v ilim = 2.00v 185 200 215 current-limit threshold (adjustable) v limit v csh _ - v csl _ v ilim = 1.00v 94 100 106 mv v csh _ - v csl _, skip = ilim = ldo5 -67 -60 -53 mv current-limit threshold (negative) v neg v csh _ - v csl _, skip = ldo5, adjustable mode, percent of current limit -120 % current-limit threshold (zero crossing) v zx v csh _ - v csl _, skip = gnd, ilim = ldo5 036mv ilim = ldo5 6 10 14 mv idle mode threshold v idle v csh _ - v csl _, skip = gnd with respect to current-limit threshold (v limit ) 20 % ilim = ldo5 2.5 5 7.5 mv idle mode threshold (low audible-noise mode) v idle v csh _ - v csl _, skip = ref with respect to current-limit threshold (v limit ) 10 % ilim leakage current ilim = gnd or ref -1 +1 ? idle mode is a trademark of maxim integrated products, inc.
max17003/max17004 high-efficiency, quad-output, main power- supply controllers for notebook computers 4 _______________________________________________________________________________________ electrical characteristics (continued) (circuit of figure 1, v in = 12v, both smps enabled, fsel = ref, skip = gnd, ilim = ldo5, fba = ldo5, i ref = i ldo5 = i outa = no load, t a = 0? to +85? , unless otherwise noted. typical values are at t a = +25?.) parameter symbol conditions min typ max units soft-start ramp time t sstart measured from the rising edge of on_ to full scale 2ms soft-stop ramp time t sstop measured from the falling edge of on_ to full scale 4ms internal fixed linear regulators ldo5 output voltage v ldo5 on5 = gnd, 6v < v in < 26v, 0 < i ldo5 < 100ma 4.85 4.95 5.10 v ldo5 undervoltage-lockout fault threshold rising edge, hysteresis = 1% (typ) 225 450 v ldo5 bootstrap switch threshold ri si ng ed g e of c s l5, hyster esi s = 1% ( typ ) 4.35 4.55 4.70 v ld o 5 bootstr ap s w i tch resi stance ld o 5 to c s l5, v c s l 5 = 5v , i l d o5 = 50m a15 short-circuit current ldo5 = gnd, on5 = gnd 225 450 ma short-circuit current (switched over to csl_) ldo5 = gnd, v csl5 > 4.7v 200 425 ma auxiliary linear regulator drva voltage range v drva 0.5 26.0 v v fba = 1.05v, v drva = 5v 0.4 drva drive current v fba = 0.965v, v drva = 5v 10 ma fba regulation threshold v fba v drva = 5v, i drva = 1ma (sink) 0.98 1.00 1.02 v fba load regulation v dra = 5v, i drva = 0.5ma to 5ma -1.2 -2.2 % outa shunt trip level rising edge 25 26 27 v fba leakage current v fba = 1.035v 0.1 +0.1 a secondary feedback regulation threshold v drva - v outa 0v dl5 pulse width 1/ 3f osc ? outa leakage current i outa v drva = v outa = 25v 50 ? reference (ref) reference voltage v ref ldo5 in regulation, i ref = 0 1.985 2.00 2.015 v reference load-regulation error v ref i ref = -5? to +50? -10 +10 mv ref lockout voltage v ref ( uvlo ) rising edge 1.8 v fault detection output overvoltage trip threshold (max17003 only) with respect to error-comparator threshold 81114% outp ut over vol tag e faul t p r op ag ati on d el ay ( m ax 17003 onl y) t ovp 50mv overdrive 10 ?
max17003/max17004 high-efficiency, quad-output, main power- supply controllers for notebook computers _______________________________________________________________________________________ 5 electrical characteristics (continued) (circuit of figure 1, v in = 12v, both smps enabled, fsel = ref, skip = gnd, ilim = ldo5, fba = ldo5, i ref = i ldo5 = i outa = no load, t a = 0? to +85? , unless otherwise noted. typical values are at t a = +25?.) parameter symbol conditions min typ max units output undervoltage protection trip threshold with respect to error-comparator threshold 65 70 75 % output undevoltage fault propagation delay t uvp 50mv overdrive 10 ? output undervoltage protection blanking time t blank from rising edge of on_ with respect to f sw 5000 6144 7000 1/f osc pgdall lower trip threshold wi th r esp ect to ei ther s m p s er r or - com p ar ator thr eshol d , hyster esi s = 1% ( typ ) -12 -10 -8 % falling edge, 50mv overdrive 10 pgdall propagation delay t pgdall rising edge, 50mv overdrive 1 ? pgdall output low voltage i sink = 1ma 0.4 v pgdall leakage current i pgdall high state, pgdall forced to 5.5v 1 ? thermal-shutdown threshold t shdn hysteresis = 15? +160 ? gate drivers dh_ gate-driver on-resistance r dh bst_ ?lx_ forced to 5v 1.3 5 dl_, high state 1.7 5 dl_ gate-driver on-resistance r dl dl_, low state 0.6 3 dh_ gate-driver source/sink current i dh dh_ forced to 2.5v, bst_ - lx_ forced to 5v 2a dl_ gate-driver source current i dl ( source ) dl_ forced to 2.5v 1.7 a dl_ gate-driver sink current i dl ( sink ) dl_ forced to 2.5v 3.3 a dh_low to dl_high 15 45 dead time t dead dl_low to dh_high 15 44 ns internal bst_ switch on- resistance r bst i bst = 10ma 5 bst_ leakage current v bst _ = 26v 2 20 a inputs and outputs rising trip level 1.1 1.6 2.2 shdn input trip level falling trip level 0.96 1 1.04 v high 2.4 ona logic input voltage hysteresis = 600mv (typ) low 0.8 v smps off level/clear fault level 0.8 delay start level 1.9 2.1 on3, on5 input voltage smps on level 2.4 v dschg_ on-resistance r dschg_ o n 3 = o n 5 = s hd n = 0; i d s c h g_ = 10m a 5 11 25 dschg_ leakage current high state, dschg_ forced to 5.5v 1 ?
max17003/max17004 high-efficiency, quad-output, main power- supply controllers for notebook computers 6 _______________________________________________________________________________________ electrical characteristics (circuit of figure 1, v in = 12v, both smps enabled, fsel = ref, skip = gnd, ilim = ldo5, fba = ldo5, i ref = i ldo5 = i outa = no load, t a = -40? to +85? , unless otherwise noted.) (note 3) parameter symbol conditions min max units input supplies (note 1) ldo5 in regulation 5.4 26.0 v in input voltage range v in in = ldo5, v csl5 < 4.4v 4.5 5.5 v v in operating supply current i in ldo5 switched over to csl5, either smps on 40 a v in standby supply current i in(stby) v in = 6v to 26v, both smps off, includes i shdn 120 a v in shutdown supply current i in(shdn) v in = 6v to 26v 20 a quiescent power consumption p q both smps on, fb3 = fb5 = ldo5; skip = gnd, v csl3 = 3.5v, v csl5 = 5.3v, v outa = 15v, p in + p csl3 + p csl5 + p outa 4.5 mw main smps controllers 3.3v output voltage in fixed mode v out3 v in = 6v to 26v, skip = fb3 = ldo5, 0 < v csh3 - v csl3 < 50mv (note 2) 3.255 3.375 v 5v output voltage in fixed mode v out5 v in = 6v to 26v, skip = fb5 = ldo5, 0 < v csh5 - v csl5 < 50mv (note 2) 4.925 5.105 v feedback voltage in adjustable mode v fb_ v in = 6v to 26v, fb3 or fb5 duty factor = 20% to 80% (note 2) 1.974 2.046 v output voltage adjust range either smps 2.0 5.5 v fb3, fb5 dual-mode threshold 3v v ldo5 - 0.4 v fsel = gnd 170 230 fsel = ref 270 330 operating frequency (note 1) f osc fsel = ldo5 425 575 khz maximum duty factor d max 97 % electrical characteristics (continued) (circuit of figure 1, v in = 12v, both smps enabled, fsel = ref, skip = gnd, ilim = ldo5, fba = ldo5, i ref = i ldo5 = i outa = no load, t a = 0? to +85? , unless otherwise noted. typical values are at t a = +25?.) parameter symbol conditions min typ max units high v ldo5 - 0.4 ref 1.65 2.35 tri-level input logic skip , fsel gnd 0.5 v skip , fsel forced to gnd or ldo5 -1 +1 input leakage current shdn forced to gnd or 26v -1 +1 ?
max17003/max17004 high-efficiency, quad-output, main power- supply controllers for notebook computers _______________________________________________________________________________________ 7 electrical characteristics (continued) (circuit of figure 1, v in = 12v, both smps enabled, fsel = ref, skip = gnd, ilim = ldo5, fba = ldo5, i ref = i ldo5 = i outa = no load, t a = -40? to +85? , unless otherwise noted.) (note 3) parameter symbol conditions min max units current limit ilim adjustment range 0.5 v ref v current-limit threshold (fixed) v limit v csh _ - v csl _, ilim = ldo5 44 56 mv v ilim = 2.00v 185 215 current-limit threshold (adjustable) v limit v csh _ - v csl _ v ilim = 1.00v 93 107 mv internal fixed linear regulators ldo5 output voltage v ldo5 on5 = gnd, 6v < v in < 26v, 0 < i ldo5 < 100ma 4.85 5.10 v ldo5 undervoltage-lockout fault threshold rising edge, hysteresis = 1% (typ) 3.7 4.1 v ldo5 bootstrap switch rising edge of csl5, hysteresis = 1% (typ) 4.30 4.75 v short-circuit current ldo5 = gnd, on5 = gnd 450 ma short-circuit current (switched over to csl_) ldo5 = gnd, v csl5 > 4.7v 200 ma auxiliary linear regulator drva voltage range v drva 0.5 26.0 v v fba = 1.05v, v drva = 5v 0.4 drva drive current v fba = 0.965v, v drva = 5v 10 ma fba regulation threshold v fba v drva = 5v, i drva = 1ma (sink) 0.98 1.02 v outa shunt trip level 25 27 v reference (ref) reference voltage v ref ldo5 in regulation, i ref = 0 1.980 2.020 v
max17003/max17004 high-efficiency, quad-output, main power- supply controllers for notebook computers 8 _______________________________________________________________________________________ electrical characteristics (continued) (circuit of figure 1, v in = 12v, both smps enabled, fsel = ref, skip = gnd, ilim = ldo5, fba = ldo5, i ref = i ldo5 = i outa = no load, t a = -40? to +85? , unless otherwise noted.) (note 3) parameter symbol conditions min typ max units fault detection o utp ut o ver vol tag e tr i p thr eshol d ( m ax 17003 onl y) with respect to error-comparator threshold 8 14 % output undervoltage protection with respect to error-comparator threshold 65 75 % pgdall lower trip threshold with respect to error-comparator threshold, hysteresis = 1% -12 -8 % pgdall output low voltage i sink = 1ma 0.4 v gate drivers dh_ gate-driver on-resistance r dh bst_ ?lx_ forced to 5v 5 dl_, high state 5 dl_ gate-driver on-resistance r dl dl_, low state 3 inputs and outputs rising trip level 1.0 2.3 shdn input trip level falling trip level 0.96 1.04 v high 2.4 ona logic input voltage hysteresis = 600mv (typ) low 0.8 v smps off level/clear fault level 0.8 delay start level 1.9 2.1 on3, on5 input voltage smps on level 2.4 v dschg_ on-resistance r dschg_ o n 3 = o n 5 = s hd n = 0; i d s c h g_ = 10m a5 25 high v ldo5 - 0.4 1a ref 1.65 2.35 tri-level input logic skip , fsel gnd 0.5 v note 1: the max17003/max17004 cannot operate over all combinations of frequency, input voltage (v in ), and output voltage. for large input-to-output differentials and high switching-frequency settings, the required on-time may be too short to maintain the regulation specifications. under these conditions, a lower operating frequency must be selected. the minimum on-time must be greater than 150ns, regardless of the selected switching frequency. on-time and off-time specifications are mea- sured from 50% point to 50% point at the dh_ pin with lx_ = gnd, v bst_ = 5v, and a 250pf capacitor connected from dh_ to lx_. actual in-circuit times may differ due to mosfet switching speeds. note 2: when the inductor is in continuous conduction, the output voltage has a dc-regulation level lower than the error-comparator threshold by 50% of the ripple. in discontinuous conduction ( skip = gnd, light load), the output voltage has a dc regula- tion level higher than the trip level by approximately 1% due to slope compensation. note 3: specifications from -40? to +85? are guaranteed by design, not production tested.
max17003/max17004 high-efficiency, quad-output, main power- supply controllers for notebook computers _______________________________________________________________________________________ 9 output voltage deviation vs. input voltage input voltage (v) output voltage deviation (%) max17003/max17004 toc07 0 4 8 12 16 20 -3 -2 -1 0 1 2 3 3.3v output 5.0v output 5v output efficiency vs. load current load current (a) efficiency (%) max17003/max17004 toc01 50 60 70 80 90 100 0.001 0.01 0.1 1 10 7v 20v skip mode pwm mode 12v 5v output efficiency vs. load current load current (a) efficiency (%) max17003/max17004 toc02 50 60 70 80 90 100 0.001 0.01 0.1 1 10 pwm mode low-noise mode skip mode 5v output voltage vs. load current load current (a) output voltage (v) max17003/max17004 toc03 0.0 1.0 2.0 3.0 4.0 5.0 4.90 4.95 5.00 5.05 5.10 skip mode low-noise mode pwm mode 3.3v output efficiency vs. load current load current (a) efficiency (%) max17003/max17004 toc04 50 60 70 80 90 100 0.001 0.01 0.1 1 10 20v skip mode pwm mode 12v 7v 3.3v output efficiency vs. load current load current (a) efficiency (%) max17003/max17004 toc05 50 60 70 80 90 100 0.001 0.01 0.1 1 10 low-noise mode skip mode pwm mode 3.3v output voltage vs. load current load current (a) output voltage (v) max17003/max17004 toc06 012345 3.24 3.27 3.30 3.33 3.36 3.39 pwm mode skip mode low-noise mode no-load input supply current vs. input voltage input voltage (v) supply current (ma) max17003/max17004 toc08 0 4 8 12 16 20 1 10 100 pwm mode skip mode low-noise mode standby and shutdown input current vs. input voltage input voltage (v) supply current ( a) max17003/max17004 toc09 0 4 8 12 16 20 1 10 100 standby (onx = gnd) shutdown (shdn = gnd) typical operating characteristics (circuit of figure 1, v in = 12v, skip = gnd, fsel = ref, t a = +25?, unless otherwise noted.)
max17003/max17004 high-efficiency, quad-output, main power- supply controllers for notebook computers 10 ______________________________________________________________________________________ 3.3v idle mode current vs. input voltage input voltage (v) idle-mode current (ma) max17003/max17004 toc10 0 4 8 12 16 20 0 1 2 3 skip mode skip = gnd low-noise mode skip = ref 3.3v switching frequency vs. load current max17003/max17004 toc11 load current (a) switching frequency (khz) 1 0.1 0.01 10 100 1000 1 0.001 10 forced-pwm low-noise skip pulse skipping reference offset voltage distribution 2v ref offset voltage (mv) sample percentage (%) max17003/max17004 toc12 -10 -6 -2 2 6 10 0 20 10 30 +85 c +25 c 50 40 sample size = 125 ldo5 output voltage vs. load current load current (ma) output voltage (v) max17003/max17004 toc13 0 20406080100 4.5 4.6 4.7 4.8 4.9 5.0 outa output voltage vs. load current load current (ma) output voltage (v) max17003/max17004 toc14 0 50 100 150 11.9 12.0 12.1 12.2 power-up sequence max17003/max17004 toc15 b a 400 s/div c d e 12v 0 0 0 5v 0 0 a. input supply, 5v/div b. ref, 1v/div c. 5v output (v out5 ), 2v/div d. ldo5, 5v/div e. pgdall, 5v/div typical operating characteristics (continued) (circuit of figure 1, v in = 12v, skip = gnd, fsel = ref, t a = +25?, unless otherwise noted.)
max17003/max17004 high-efficiency, quad-output, main power- supply controllers for notebook computers ______________________________________________________________________________________ 11 typical operating characteristics (continued) (circuit of figure 1, v in = 12v, skip = gnd, fsel = ref, t a = +25?, unless otherwise noted.) soft-start waveform max17003/max17004 toc16 b a 400 s/div c d e f g 0 0 0 0 0 0 2v 0 a. aux ldo output (v outa ), 5v/div b. 5v output (v out5 ), 2v/div c. 3.3v output (v out3 ), 2v/div d. pgdall, 5v/div on3 = on5, ldo5 e. ref, 2v/div f. dl5, 5v/div g. shdn, 5v/div smps delayed startup sequence (on3 = ref) max17003/max17004 toc17 b a 1ms/div c d e 3.3v 0 5v 0 0 0 3.3v 0 a. on5, 5v/div b. 5v output (v out5 ), 5v/div c. pgood5, 5v/div on3 = ref d. 3.3v output (v out3 ), 5v/div e. pgood3, 5v/div smps delayed startup sequence (on5 = ref) max17003/max17004 toc18 b a 1ms/div c d e 3.3v 0 5v 0 0 0 3.3v 0 a. on3, 5v/div b. 5v output (v out5 ), 5v/div c. pgood5, 5v/div on5 = ref d. 3.3v output (v out3 ), 5v/div e. pgood3, 5v/div smps shutdown waveform max17003/max17004 toc19 b a 4ms/div c d e f 3.3v 3.3v 5v 5v 5v 0 0 0 0 a. on3, on5, 5v/div b. 5v output (v out5 ), 2v/div c. 3.3v output (v out3 ), 2v/div d. pgdall, 5v/div e. dl5, 5v/div f. dl3, 5v/div out5 load transient max17003/max17004 toc20 b a 20 s/div c d 5a 5.1v 1a 5a 12v 5.0v 4.9v 0 1a a. i out5 = 1a to 5a, 5a/div b. v out5 , 50mv/div c. inductor current, 5a/div d. lx5, 10v/div out3 load transient max17003/max17004 toc21 b a 20 s/div c d 3a 3.35v 1a 3a 12v 3.30v 3.25v 0 1a a. i out3 = 1a to 3a, 5a/div b. v out3 , 50mv/div c. inductor current, 5a/div d. lx3, 10v/div
max17003/max17004 high-efficiency, quad-output, main power- supply controllers for notebook computers 12 ______________________________________________________________________________________ ld05 load transient max17003/max17004 toc25 a 20 s/div b 5.00v 4.95v 100ma 0 a. ldo5 output, 50mv/div b. load current, 50ma/div max17003/max17004 toc22 b a 40 s/div c d 3.3v 3.35v 0 2a 12v 3.25v 0 0 a. skip, 5v/div b. 3.3v output (v out3 ), 100mv/div 0.5a load c. inductor current, 2a/div d. lx3, 10v/div skip transition output overvoltage fault protection (max17003 only) max17003/max17004 toc23 b a 100 s/div c d e 5v 3.3 0 5v 5v 5v 0 0 0 a. 5v output (v out5 ), 2v/div b. 3.3v output (v out3 ), 2v/div c. dl3, 5v/div r load5 = 5 d. dl5, 5v/div e. pgdall, 5v/div output undervoltage (short-circuit) fault protection max17003/max17004 toc24 b a 4ms/div c d 5v 3.3v 0 5v 5v 0 0 a. 3.3v output (v out3 ), 2v/div b. 5v output (v out5 ), 2v/div c. pgdall, 5v/div d. dl3, 5v/div ldoa load transient max17003/max17004 toc26 a 20 s/div c b 5v 15.0v 14.5v 12.0v 11.9v 0 a. load fet gate, 5v/div b. aux ldo input, 0.5v/div 0 to 150ma load transient c. aux ldo output (v outa ), 0.1v/div typical operating characteristics (continued) (circuit of figure 1, v in = 12v, skip = gnd, fsel = ref, t a = +25?, unless otherwise noted.)
max17003/max17004 high-efficiency, quad-output, main power- supply controllers for notebook computers ______________________________________________________________________________________ 13 pin name function 1 ona auxiliary ldo enable input. when ona is pulled low, outa is high impedance and the secondary feedback control is disabled. when ona is driven high, the controller enables the auxiliary ldo. 2 drva auxiliary ldo transistor base driver. connect drva to the base of a pnp power transistor. add a 680 pullup resistor between the base and emitter. 3 ilim peak current-limit threshold adjustment. the current-limit threshold defaults to 50mv if ilim is pulled up to ldo5. in adjustable mode, the current-limit threshold across csh_ and csl_ is precisely 1/10th the voltage seen at ilim over a 0.5v to 2.0v range. the logic threshold for switchover to the 50mv default value is approximately v ldo5 - 1v. 4 shdn shutdown control input. the device enters its 8? supply-current shutdown mode if v shdn is less than the shdn input falling-edge trip level and does not restart until v shdn is greater than the shdn input rising- edge trip level. connect shdn to v in for automatic startup. shdn can be connected to v in through a resistive voltage-divider to implement a programmable undervoltage lockout. 5 on3 3.3v smps enable input. driving on3 high enables the 3.3v smps, while pulling on3 low disables the 3.3v smps. if on3 is connected to ref, the 3.3v smps starts after the 5v smps reaches regulation (delayed start). drive on3 below the clear fault level to reset the fault latch. 6 on5 5v smps enable input. driving on5 high enables the 5v smps, while pulling on5 low disables the 5v smps. if on5 is connected to ref, the 5v smps starts after the 3.3v smps reaches regulation (delayed start). drive on5 below the clear fault level to reset the fault latch. 7 ref 2.0v reference voltage output. bypass ref to analog ground with a 0.1? or greater ceramic capacitor. the reference sources up to 50? for external loads. loading ref degrades output-voltage accuracy according to the ref load-regulation error. the reference shuts down when the system pulls shdn low. 8 gnd analog ground. connect the exposed backside pad to gnd. 9 fsel frequency select input. this three-level logic input sets the controllers?switching frequency. connect to ldo5, ref, or gnd to select the following typical switching frequencies: ldo5 = 500khz, ref = 300khz, gnd = 200khz. 10 skip pulse-skipping control input. connect to ldo5 for low-noise, forced-pwm operation. connect to ref for automatic, low-noise, pulse-skipping operation at light loads. connect to gnd for automatic, high-efficiency, pulse-skipping operation at light loads. startup is always in the low-noise, pulse-skipping mode (i.e., same as skip = ref setting), regardless of the skip setting. the skip setting takes effect once the respective smps is in re g ulation. 11 fb5 feedback input for the 5v smps. connect to ldo5 for the preset 5v output. in adjustable mode, fb5 regulates to 2v. 12 csh5 p osi ti ve c ur r ent- s ense inp ut for the 5v s m p s . c onnect to the p osi ti ve ter m i nal of the cur r ent- sense el em ent. fi g ur e 7 d escr i b es tw o d i ffer ent cur r ent- sensi ng op ti ons? usi ng accur ate sense r esi stor s or l ossl ess i nd uctor d c r sensi ng . 13 csl5 output-sense and negative current-sense input for the 5v smps. when using the internal preset 5v feedback-divider (fb5 = ldo5), the controller uses csl5 to sense the output voltage. connect to the negative terminal of the current-sense element. csl5 also serves as the bootstrap input for ldo5. for the max17003, place a schottky diode from csl5 to gnd to prevent csl5 from going below -7v. 14 dschg5 open-drain discharge input for the 5v smps. dschg5 is pulled low when on5 is low, discharging the smps5 output. dschg5 is also low under fault conditions. connect a resistor from dschg5 to the smps5 output. limit the peak discharge current to less than 100ma: where r dschg5(min) is 5 , taken from the electrical characteristics . pin description r v ma r dis out dschg min 5 5 5 100 ? ()
max17003/max17004 high-efficiency, quad-output, main power- supply controllers for notebook computers 14 ______________________________________________________________________________________ pin name function 15 bst5 boost flying capacitor connection for the 5v smps. the max17003/max17004 include an internal boost switch connected between ldo5 and bst5. connect to an external capacitor as shown in figure 1. 16 dh5 high-side gate-driver output for the 5v smps. dh5 swings from lx5 to bst5. 17 lx5 inductor connection for the 5v smps. connect lx5 to the switched side of the inductor. lx5 serves as the lower supply rail for the dh5 high-side gate driver. 18 dl5 low-side gate-driver output for the 5v smps. dl5 swings from pgnd to ldo5. 19 pgnd power ground 20 ldo5 5v internal linear-regulator output. bypass with 4.7? minimum (1?/25ma). provides at least 100ma for the dl_ low-side gate drivers, the dh_ high-side drivers through the bst switches, the pwm controller, logic, reference, and external loads. if csl5 is greater than 4.5v and soft-start is complete, the linear regulator shuts down, and ldo5 connects to csl5 through a 1 switch rated for loads up to 200ma. 21 in input of the startup circuitry and the ldo5 internal 5v linear regulator. bypass to pgnd with a 0.22? or greater ceramic capacitor close to the ic. 22 pgdall open-drain power-good output for smps3 and smps5. pgdall is pulled low if either smps3 or smps5 output drops more than 10% (typ) below the normal regulation point, or if either on3 or on5 are low. pgdall becomes high impedance when both smps3 and smps5 are in regulation. 23 dl3 low-side gate-driver output for the 3.3v smps. dl3 swings from pgnd to ldo5. 24 lx3 inductor connection for the 3.3v smps. connect lx3 to the switched side of the inductor. lx3 serves as the lower supply rail for the dh3 high-side gate driver. 25 dh3 high-side gate-driver output for the 3.3v smps. dh3 swings from lx3 to bst3. 26 bst3 boost flying capacitor connection for the 3.3v smps. the max17003/max17004 include an internal boost switch connected between ldo5 and bst3. connect to an external capacitor as shown in figure 1. 27 dschg3 open-drain discharge output for the 3.3v smps. dschg3 is pulled low when on3 is low, discharging the smps3 output. dschg3 is also low under fault conditions. connect a resistor from dschg3 to the smps3 output. limit the peak discharge current to less than 100ma: where r dschg3(min) is 5 , taken from the electrical characteristics . 28 csl3 output sense and negative current sense for the 3.3v smps. when using the internal preset 3.3v feedback divider (fb3 = ldo5), the controller uses csl3 to sense the output voltage. connect to the negative terminal of the current-sense element. 29 csh3 positive current-sense input for the 3.3v smps. connect to the positive terminal of the current-sense element. figure 7 describes two different current-sensing options?sing accurate sense resistors or lossless inductor dcr sensing. 30 fb3 feedback input for the 3.3v smps. connect to ldo5 for fixed 3.3v output. in adjustable mode, fb3 regulates to 2v. pin description (continued) r v ma r dis out dschg min 3 3 3 100 ? ()
max17003/max17004 high-efficiency, quad-output, main power- supply controllers for notebook computers ______________________________________________________________________________________ 15 pin name function 31 fba auxiliary ldo feedback input. connect a resistive voltage-divider from outa to analog ground to adjust the auxiliary linear-regulator output voltage. fba regulates at 1v. 32 outa adjustable auxiliary linear-regulator output. bypass outa to gnd with 1? or greater capacitor (1?/25ma). when drva < outa, the secondary feedback control triggers the dl5 for 1? forcing the controller to recharge the auxiliary storage capacitor. when drva exceeds 25v, the max17003/max17004 enable a 10ma shunt on outa, preventing the storage capacitor from rising to unsafe levels due to the transformer? leakage inductance. pulling ona high enables the linear-regulator driver and the secondary feedback control. ep ep exposed pad. connect the exposed backside pad to analog ground. pin description (continued) table 1. component selection for standard applications component 300khz 5v at 5a 3.3v at 5a 500khz 5v at 3a 3.3v at 5a input voltage v in = 7v to 24v v in = 7v to 24v c in_ , input capacitor (3) 10?, 25v taiyo yuden tmk432bj106km (3) 10?, 25v taiyo yuden tmk432bj106km 5v output c out5 , output capacitor 2x 100?, 6v, 35m sanyo 6tpe100mazb 2x 100?, 6v, 35m sanyo 6tpe100mazb l5/t5 inductor/transformer 6.8?, 6.4a, 18m (max) 1:2 sumida 4749-t132 n h5 high-side mosfet fairchild semiconductor fds6612a international rectifier irf7807v fairchild semiconductor fds6612a international rectifier irf7807v n l5 low-side mosfet fairchild semiconductor fds6670s international rectifier irf7807vd1 fairchild semiconductor fds6670s international rectifier irf7807vd1 3v output c out3 , output capacitor 2x 150?, 4v, 35m sanyo 4tpe150mazb 2x 100?, 6v, 35m sanyo 6tpe100mazb l3, inductor 5.8?, 8.6a, 16.2m sumida corh127/ld-5r8nc 3.9?, 6.5a, 15m sumida cdrh124-3r9nc n h3 high-side mosfet fairchild semiconductor fds6612a international rectifier irf7807v fairchild semiconductor fds6612a international rectifier irf7807v n l3 low-side mosfet fairchild semiconductor fds6670s international rectifier irf7807vd1 fairchild semiconductor fds6670s international rectifier irf7807vd1
max17003/max17004 high-efficiency, quad-output, main power- supply controllers for notebook computers 16 ______________________________________________________________________________________ max17003 max17004 power ground analog ground dh5 in c ldo5 4.7 f bst5 input (v in ) csh5 csl5 dl5 lx5 fb5 c in see table 1 for component specifications. ilim fsel ref (300khz) smps power-good 3.3v pwm output 5v pwm output c ref 0.22 f n l2 t1 n h2 c bst2 0.1 f d l2 c out5 pgdall n l1 l1 n h1 c bst1 0.1 f d l1 c out3 dh3 bst3 dl3 lx3 csh3 csl3 fb3 r7 100k r9 47 r8 47 connect to 5v or 3.3v 5v pwm output ldo5 3.3v pwm output pgnd ona on3 on5 shdn off on d1 secondary output c aux 4.7 f dschg3 dschg5 4 5 6 7 3 30 11 28 29 13 12 gnd 8 19 18 17 15 16 21 23 24 26 25 1 9 10 14 27 22 5v ldo output 20 ref c in outa fba c ldoa 4.7 f 12v ldo output r5 110k r6 10k 32 31 drva 2 secondary output r1 6.96k r2 3.48k c1 0.22 f r3 10.5k r4 4.02k c2 0.22 f r10 680 c3 1000pf c4 1000pf skip figure 1. standard application circuit
max17003/max17004 high-efficiency, quad-output, main power- supply controllers for notebook computers ______________________________________________________________________________________ 17 detailed description the max17003/max17004 standard application circuit (figure 1) generates the 5v/5a and 3.3v/5a typical of the main supplies in a notebook computer. the input supply range is 7v to 24v. see table 1 for component selec- tions, while table 2 lists the component manufacturers. the max17003/max17004 contain two interleaved, fixed-frequency, step-down controllers designed for low- voltage power supplies. the optimal interleaved archi- tecture guarantees out-of-phase operation, reducing the input capacitor ripple. one internal ldo generates the keep-alive 5v power. the max17003/max17004 have an auxiliary ldo with an adjustable output for generating either the 3.3v keep-alive supply or regulating the low- power 12v system supply. fixed 5v linear regulator (ldo5) an internal linear regulator produces a preset 5v low- current output. ldo5 powers the gate drivers for the external mosfets, and provides the bias supply required for the smps analog controller, reference, and logic blocks. ldo5 supplies at least 100ma for exter- nal and internal loads, including the mosfet gate drive, which typically varies from 5ma to 50ma, depending on the switching frequency and external mosfets selected. bypass ldo5 with a 4.7? or greater ceramic capacitor (1? per 25ma of load) to guarantee stability under the full-load conditions. the max17003/max17004 switch-mode power supplies (smps) require a 5v bias supply in addition to the high- power input supply (battery or ac adapter). this 5v bias supply is generated by the controller? internal 5v linear regulator (ldo5). this bootstrapped ldo allows the controller to power up independently. the gate-driver input supply is connected to the fixed 5v linear-regulator output (ldo5). therefore, the 5v ldo supply must pro- vide ldo5 (pwm controller) and the gate-drive power, so the maximum supply current required is: i bias = i cc + f sw (q g(low) + q g(high) ) = 5ma to 50ma (typ) where i cc is 0.7ma (typ), f sw is the switching frequency, and q g(low) and q g(high) are the mosfet data sheet? total gate-charge specification limits at v gs = 5v. smps to ldo bootstrap switchover when the 5v main output voltage is above the ldo5 bootstrap-switchover threshold and has completed soft-start, an internal 1 (typ) p-channel mosfet shorts csl5 to ldo5, while simultaneously shutting down the ldo5 linear regulator. this bootstraps the device, powering the internal circuitry and external loads from the 5v smps output (csl5), rather than through the linear regulator from the battery. boot- strapping reduces power dissipation due to gate charge and quiescent losses by providing power from a 90%-efficient switch-mode source, rather than from a much-less-efficient linear regulator. the current capa- bility increases from 100ma to 200ma when the ldo5 output is switched over to csl5. when on5 is pulled low, the controller immediately disables the bootstrap switch and reenables the 5v ldo. reference (ref) the 2v reference is accurate to ?% over temperature and load, making ref useful as a precision system re- ference. bypass ref to gnd with a 0.1? or greater ceramic capacitor. the reference sources up to 50? and sinks 5? to support external loads. if highly accu- rate specifications are required for the main smps out- put voltages, the reference should not be loaded. loading the reference reduces the ldo5, csl5 (out5), csl3 (out3), and outa output voltages slightly because of the reference load-regulation error. system enable/shutdown ( shdn ) drive shdn below the precise shdn input falling-edge trip level to place the max17003/max17004 in its low- power shutdown state. the controller consumes only 8? of quiescent current while in shutdown mode. when shutdown mode activates, the reference turns off after the controller completes the shutdown sequence table 2. component suppliers supplier website avx www.avx.com central semiconductor www.centralsemi.com fairchild www.fairchildsemi.com international rectifier www.irf.com kemet www.kemet.com nec/tokin www.nec-tokin.com panasonic www.panasonic.com/industrial philips www.philips.com pulse www.pulseeng.com renesas www.renesas.com sanyo www.edc.sanyo.com sumida www.sumida.com taiyo yuden www.t-yuden.com tdk www.component.tdk.com toko www.tokoam.com vishay (dale, siliconix) www.vishay.com
max17003/max17004 high-efficiency, quad-output, main power- supply controllers for notebook computers 18 ______________________________________________________________________________________ ref r r fb3 2.0v ref dh5 bst5 lx5 ldo5 dl5 pwm5 controller (figure 3) dh3 bst3 lx3 ldo5 dl3 pwm3 controller (figure 3) pgnd fb decode (figure 5) on3 in fsel fb decode (figure 5) fb5 on5 csh5 csl5 ilim csh3 csl3 pgdall power-good and fault protection (figure 6) internal fb fault fba outa drva ona skip 5v linear regulator ldo5 auxiliary linear regulator gnd ldo bypass circuitry osc secondary feedback shdn dschg3 dschg5 ldo5 max17003 max17004 figure 2. functional diagram
max17003/max17004 high-efficiency, quad-output, main power- supply controllers for notebook computers ______________________________________________________________________________________ 19 making the threshold to exit shutdown less accurate. to guarantee startup, drive shdn above 2v ( shdn input rising-edge trip level). for automatic shutdown and startup, connect shdn to v in . the accurate 1v falling- edge threshold on shdn can be used to detect a spe- cific input voltage level and shut the device down. once in shutdown, the 1.6v rising-edge threshold activates, providing sufficient hysteresis for most applications. smps por, uvlo, and soft-start power-on reset (por) occurs when ldo5 rises above approximately 1v, resetting the undervoltage, overvolt- age, and thermal-shutdown fault latches. the por cir- cuit also ensures that the low-side drivers are pulled high until the smps controllers are activated. figure 2 is the max17003/max17004 block diagram. the ldo5 input undervoltage-lockout (uvlo) circuitry inhibits switching if the 5v bias supply (ldo5) is below its 4v uvlo threshold. once the 5v bias supply (ldo5) rises above this input uvlo threshold and the smps controllers are enabled (on_ driven high), the smps controllers start switching, and the output volt- ages begin to ramp up using soft-start. if the ldo5 voltage drops below the uvlo threshold, the controller stops switching and pulls the low-side gate drivers low until the ldo5 voltage recovers or drops below the por threshold. the internal soft-start gradually increases the feedback voltage with a 1v/ms slew rate. therefore, the outputs reach their nominal regulation voltage 2ms after the smps controllers are enabled (see the soft-start waveform in the typical operating characteristics ). this gradual slew rate effectively reduces the input surge current by minimizing the current required to charge the output capacitors (i out = i load + c out x v out(nom) /t slew ). smps enable controls (on3, on5) on3 and on5 control smps power-up sequencing. on3 or on5 rising above 2.4v enables the respective outputs. on3 or on5 falling below 1.6v disables the respective outputs. driving on_ below 0.8v clears the overvoltage, undervoltage, and thermal fault latches. smps power-up sequencing connecting on3 or on5 to ref forces the respective outputs off while the other output is below regulation and starts after that output regulates. the second smps remains on until the first smps turns off, the device shuts down, a fault occurs, or ldo5 goes into uvlo. both supplies begin their power-down sequence immediately when the first supply turns off. table 3. operating mode truth table inputs* outputs mode shdn on5 on3 ldo5 5v smps 3v smps shutdown mode low x x off off off standby mode high low low on off, dschg5 low off, dschg3 low normal operation high high high on on on 3.3v smps active high low high on off, dschg5 low on 5v smps active high high low off ldo5 to csl5 bypass switch enabled on off, dschg3 low normal operation (delayed 5v smps startup) high ref high off ldo5 to csl5 bypass switch enabled on power-up after 3.3v smps is in regulation on normal operation (delayed 3.3v smps startup) high high ref off ldo5 to csl5 bypass switch enabled on on power-up after 5v smps is in regulation * shdn is an accurate, low-voltage logic input with 1v falling-edge threshold voltage and 1.6v rising-edge threshold voltage. on3 and on5 are tri-level cmos logic inputs, a logic-low voltage is less than 0.8v, a logic-high voltage is greater than 2.4v, and the mid- dle-logic level is between 1.7v and 2.3v (see the electrical characteristics table).
max17003/max17004 high-efficiency, quad-output, main power- supply controllers for notebook computers 20 ______________________________________________________________________________________ output discharge (soft-discharge) when the switching regulators are disabled?hen on_ or shdn is pulled low, or when an output undervoltage fault occurs?he internal soft-discharge gradually decreases the output voltage by pulling dschg_ low (see the smps shutdown waveform in the typical operating characteristics ). this slowly discharges the output capacitance, eliminating the nega tive output volt- ages caused by quickly discharging the output through the inductor and low-side mosfet. both smps con- trollers contain separate soft-shutdown circuits. fixed-frequency, current-mode pwm controller the heart of each current-mode pwm controller is a multi-input, open-loop comparator that sums two sig- nals: the output-voltage error signal with respect to the reference voltage and the slope-compensation ramp (figure 3). the max17003/max17004 use a direct- summing configuration, approaching ideal cycle-to- cycle control over the output voltage without a traditional error amplifier and the phase shift associated with it. s r q r s q dh driver dl driver slope comp soft- start/stop peak current limit fsel from fb (see figure 5) ref csl_ csh_ idle mode current 0.1 x v limit outa drva one-shot pgnd gnd on_ neg current limit zero crossing ilim a = 1/10 a = 1.2 osc tri-level decode 5v smps only 0.2 x v limit skip figure 3. pwm controller functional diagram
max17003/max17004 high-efficiency, quad-output, main power- supply controllers for notebook computers ______________________________________________________________________________________ 21 frequency selection (fsel) the fsel input selects the pwm mode switching fre- quency. table 4 shows the switching frequency based on fsel connection. high-frequency (500khz) operation optimizes the application for the smallest component size, trading off efficiency due to higher switching losses. this may be acceptable in ultraportable devices where the load currents are lower. low-frequency (200khz) operation offers the best overall efficiency at the expense of component size and board space. forced-pwm mode the low-noise forced-pwm mode ( skip = ldo5) dis- ables the zero-crossing comparator, which controls the low-side switch on-time. this forces the low-side gate- drive waveform to be constantly the complement of the high-side gate-drive waveform, so the inductor current reverses at light loads while dh_ maintains a duty factor of v out /v in . the benefit of forced-pwm mode is to keep the switching frequency fairly constant. however, forced- pwm operation comes at a cost: the no-load 5v supply current remains between 20ma to 50ma, depending on the external mosfets and switching frequency. forced-pwm mode is most useful for avoiding audio- frequency noise and improving load-transient response. since forced-pwm operation disables the zero-crossing comparator, the inductor current revers- es under light loads. light-load operation control ( skip ) the max17003/max17004 include a light-load operat- ing mode control input ( skip ) used to enable or dis- able the zero-crossing comparator for both switching regulators. when the zero-crossing comparator is enabled, the regulator forces dl_ low when the cur- rent-sense inputs detect zero inductor current. this keeps the inductor from discharging the output capaci- tors and forces the regulator to skip pulses under light- load conditions to avoid overcharging the output. when the zero-crossing comparator is disabled, the regulator is forced to maintain pwm operation under light-load conditions (forced-pwm). idle mode current-sense threshold when pulse-skipping mode is enabled, the on-time of the step-down controller terminates when the output voltage exceeds the feedback threshold and when the current- sense voltage exceeds the idle-mode current-sense threshold. under light-load conditions, the on-time dura- tion depends solely on the idle mode current-sense threshold, which is 20% ( skip = gnd) of the full-load current-limit threshold set by ilim, or the low-noise cur- rent-sense threshold, which is 10% ( skip = ref) of the full-load current-limit threshold set by ilim. this forces the controller to source a minimum amount of power with each cycle. to avoid overcharging the output, another on-time cannot begin until the output voltage drops below the feedback threshold. since the zero-crossing comparator prevents the switching regulator from sinking current, the controller must skip pulses. therefore, the controller regulates the valley of the output ripple under light-load conditions. automatic pulse-skipping crossover in skip mode, an inherent automatic switchover to pfm takes place at light loads (figure 4). this switchover is affected by a comparator that truncates the low-side switch on-time at the inductor current? zero crossing. the zero-crossing comparator senses the inductor cur- rent across csh_ to csl_. once (v csh _ - v csl _) drops below the 3mv zero-crossing, current-sense threshold, the comparator forces dl_ low (figure 3). this mechanism causes the threshold between pulse- skipping pfm and nonskipping pwm operation to coin- cide with the boundary between continuous and fsel switching frequency (khz) ldo5 500 ref 300 gnd 200 table 4. fsel configuration table i pk inductor current time 0 on-time i load = i pk /2 t on(skip) = v out v in f osc figure 4. pulse-skipping/discontinuous crossover point
max17003/max17004 high-efficiency, quad-output, main power- supply controllers for notebook computers 22 ______________________________________________________________________________________ discontinuous inductor-current operation (also known as the ?ritical conduction?point). the load-current level at which pfm/pwm crossover occurs, i load(skip) , is given by: the switching waveforms may appear noisy and asyn- chronous when light loading causes pulse-skipping operation, but this is a normal operating condition that results in high light-load efficiency. trade-offs in pfm noise vs. light-load efficiency are made by varying the inductor value. generally, low inductor values produce a broader efficiency vs. load curve, while higher values result in higher full-load efficiency (assuming that the coil resistance remains fixed) and less output-voltage ripple. drawbacks of using higher inductor values include larger physical size and degraded load-tran- sient response (especially at low input-voltage levels). output voltage dc output accuracy specifications in the electrical characteristics table refer to the error comparator? threshold. when the inductor continuously conducts, the max17003/max17004 regulate the peak of the out- put ripple, so the actual dc output voltage is lower than the slope-compensated trip level by 50% of the output ripple voltage. for pwm operation (continuous conduc- tion), the output voltage is accurately defined by the fol- lowing equation: where v nom is the nominal output voltage, a slope equals 1%, and v ripple is the output ripple voltage (v ripple = esr x i inductor , as described in the output capacitor selection section). in discontinuous conduction (i out < i load(skip) ), the max17003/max17004 regulate the valley of the output ripple, so the output voltage has a dc regulation level higher than the error-comparator threshold. for pfm operation (discontinuous conduction), the output volt- age is approximately defined by the following equation: where v nom is the nominal output voltage, f osc is the maximum switching frequency set by the internal oscil- lator, f sw is the actual switching frequency, and i idle is the idle mode inductor current when pulse skipping . connect fb3 and fb5 to ldo5 to enable the fixed smps output voltages (3.3v and 5v, respectively), set by a preset, internal resistive voltage-divider connected between the output (csl_) and analog ground. connect a resistive voltage-divider at fb_ between the output (csl_) and gnd to adjust the respective output voltage between 2v and 5.5v (figure 5). choose r fblo (resistance from fb to gnd) to be approximately 10k and solve for r fbhi (resistance from the output to fb) using the equation: where v fb_ = 2v nominal. when adjusting both output voltages, set the 3.3v smps lower than the 5v smps. ldo5 connects to the 5v output (csl5) through an internal switch only when csl5 is above the ldo5 bootstrap threshold (4.5v) and the soft-start sequence for the csl5 side has com- pleted. bootstrapping works most effectively when the fixed output voltages are used. once ldo5 is boot- strapped from csl5, the internal 5v linear regulator turns off. this reduces the internal power dissipation and improves efficiency at higher input voltages. current-limit protection (ilim) the current-limit circuit uses differential current-sense inputs (csh_ and csl_) to limit the peak inductor cur- rent. if the magnitude of the current-sense signal exceeds the current-limit threshold, the pwm controller turns off the high-side mosfet (figure 3). the actual rr v v fbhi fblo out fb =? ? ? ? ? ? ? _ _ 1 vv f f i esr out pfm nom sw osc idle () =+ ? ? ? ? ? ? 1 2 vv av v v out pwm nom slope ripple in ripple () =? ? ? ? ? ? ? ? ? ? ? ? ? ? 1 2 i vv v vf l load skip in out out in osc () () = ? 2 out to error amplifier ldo5 9r r fb fixed output fb = ldo5 adjustable output figure 5. dual mode feedback decoder
max17003/max17004 high-efficiency, quad-output, main power- supply controllers for notebook computers ______________________________________________________________________________________ 23 maximum load current is less than the peak current- limit threshold by an amount equal to half of the induc- tor ripple current. therefore, the maximum load capability is a function of the current-sense resistance, inductor value, switching frequency, and duty cycle (v out /v in ). in forced-pwm mode, the max17003/max17004 also implement a negative current limit to prevent excessive reverse inductor currents when v out is sinking current. the negative current-limit threshold is set to approxi- mately 120% of the positive current limit and tracks the positive current limit when ilim is adjusted. connect ilim to ldo5 for the 50mv default threshold, or adjust the current-limit threshold with an external resistor-divider at ilim. use a 2? to 20? divider cur- rent for accuracy and noise immunity. the current-limit threshold adjustment range is from 50mv to 200mv. in the adjustable mode, the current-limit threshold voltage equals precisely 1/10th the voltage seen at ilim. the logic threshold for switchover to the default value is approximately v ldo5 - 1v. carefully observe the pcb layout guidelines to ensure that noise and dc errors do not corrupt the differential current-sense signals seen by csh_ and csl_. place the ic close to the sense resistor with short, direct traces, making a kelvin-sense connection to the cur- rent-sense resistor. mosfet gate drivers (dh_, dl_) the dh_ and dl_ drivers are optimized for driving moderate-sized high-side and larger low-side power mosfets. this is consistent with the low duty factor seen in notebook applications, where a large v in - v out differential exists. the high-side gate drivers (dh_) source and sink 2a, and the low-side gate dri- vers (dl_) source 1.7a and sink 3.3a. this ensures robust gate drive for high-current applications. the dh_ floating high-side mosfet drivers are powered by charge pumps at bst_ while the dl_ synchronous-rec- tifier drivers are powered directly by the fixed 5v linear regulator (ldo5). adaptive dead-time circuits monitor the dl_ and dh_ drivers and prevent either fet from turning on until the other is fully off. the adaptive driver dead-time allows operation without shoot-through with a wide range of mosfets, minimizing delays and maintaining efficiency. there must be a low-resistance, low-inductance path from the dl_ and dh_ drivers to the mosfet gates for the adaptive dead-time circuits to work properly; other- wise, the sense circuitry in the max17003/max17004 interprets the mosfet gates as ?ff?while charge actu- ally remains. use very short, wide traces (50 mils to 100 mils wide if the mosfet is 1in from the driver). the internal pulldown transistor that drives dl_ low is robust, with a 0.6 (typ) on-resistance. this helps prevent dl_ from being pulled up due to capacitive coupling from the drain to the gate of the low-side mosfets when the inductor node (lx_) quickly switches from ground to v in . applications with high input voltages and long inductive driver traces may require additional gate-to-source capacitance to ensure fast-rising lx_ edges do not pull up the low-side mosfets gate, causing shoot-through currents. the capacitive coupling between lx_ and dl_ created by the mosfet? gate-to-drain capacitance (c gd = c rss ), gate-to-source capacitance (c gs = c iss - c gd ), and additional board parasitics should not exceed the following minimum threshold: lot-to-lot variation of the threshold voltage may cause problems in marginal designs. power-good output (pgdall) pgdall is the open-drain output of a comparator that continuously monitors both smps output voltages for undervoltage conditions. pgdall is actively held low in shutdown ( shdn = gnd), during soft-start, and soft- shutdown, and when either smps is disabled (either vv c c gs th in rss iss () > ? ? ? ? ? ? por enable ovp enable uvp power-good fault 0.9 x int ref_ fault latch 0.7 x int ref_ 1.11 x int ref_ 6144 clk power-good fault protection internal fb figure 6. power-good and fault protection
max17003/max17004 high-efficiency, quad-output, main power- supply controllers for notebook computers 24 ______________________________________________________________________________________ on3 or on5 low). once the soft-start sequence termi- nates, pgdall becomes high impedance as long as both smps outputs are above 90% of the nominal regu- lation voltage set by fb. pgdall goes low once either smps output drops 10% below its nominal regulation point, an smps output overvoltage fault occurs, or on_ or shdn is low. for a logic-level pgdall output volt- age, connect an external pullup resistor between pgdall and ldo5. a 100k pullup resistor works well in most applications. fault protection output overvoltage protection (ovp) max17003 only if the output voltage of either smps rises above 111% of its nominal regulation voltage and the ovp protection is enabled, the controller sets the fault latch, pulls pgdall low, shuts down the smps controllers that tripped the fault, and immediately pulls dh_ low and forces dl_ high. this turns on the synchronous-rectifier mosfets with 100% duty, rapidly discharging the out- put capacitors and clamping both outputs to ground. however, immediately latching dl_ high typically caus- es slightly negative output voltages due to the energy stored in the output lc at the instant the ovp occurs. if the load cannot tolerate a negative voltage, place a power schottky diode across the output to act as a reverse-polarity clamp. if the condition that caused the overvoltage persists (such as a shorted high-side mos- fet), the battery blows. the other output is shut down using the soft-discharge feature with dl_ forced low. cycle ldo5 below 1v or toggle either on3, on5, or shdn to clear the fault latch and restart the smps con- trollers. output undervoltage protection (uvp) each smps controller includes an output uvp protection circuit that begins to monitor the output 6144 clock cycles (1/f osc ) after that output is enabled (on_ pulled high). if either smps output voltage drops below 70% of its nominal regulation voltage and the uvp protection is enabled, the uvp circuit sets the fault latch, pulls pgdall low, and shuts down both controllers using the soft-discharge feature with dl_ forced low. cycle ldo5 below 1v or toggle either on3, on5, or shdn to clear the fault latch and restart the smps controllers. thermal-fault protection the max17003/max17004 feature a thermal fault-pro- tection circuit. when the junction temperature rises above +160 c, a thermal sensor activates the fault latch, pulls pgdall low, and shuts down both smps controllers using the soft-discharge feature with dl_ forced low. toggle either on3, on5, or shdn to clear the fault latch and restart the controllers after the junc- tion temperature cools by 15 c. mode condition comment power-up ldo5 < uvlo threshold transitions to discharge mode after v in por and after ref becomes valid. ldo5, ref remain active. dl_ is low. run shdn = high, on3 or on5 enabled normal operation. output overvoltage (ovp) protection (max17003) either output > 111% of nominal level exited by por or cycling shdn , on3, or on5. output undervoltage protection (uvp) either output < 70% of nominal level, uvp is enabled 6144 clock cycles (1/f osc ) after the output is enabled exited by por or cycling shdn , on3, or on5. standby on5 and on3 < startup threshold, shdn = high dl_ stays low. ldo5 active. shutdown shdn = low all circuitry off. thermal shutdown t j > +160? exited by por or cycling shdn , on3, or on5. dl3 and dl5 go low before ldo5 turns off. switchover fault excessive current on ldo5 switchover transistors exited by por or cycling shdn , on3, or on5. table 5. operating modes truth table
max17003/max17004 high-efficiency, quad-output, main power- supply controllers for notebook computers ______________________________________________________________________________________ 25 auxiliary ldo detailed description the m ax17003/max17004 include an auxiliary linear regulator (outa) that can be configured for 12v, ideal for pcmcia power requirements, and for biasing the gates of load switches in a portable device. outa can also be configured for outputs from 1v to 23v. the auxiliary regu- lator has an independent on/off control, allowing it to be shut down when not needed, reducing power con- sumption when the system is in a low-power state. a flyback-winding control loop regulates a secondary winding output, improving cross-regulation when the pri- mary output is lightly loaded or when there is a low input- output differential voltage. if v drva < v outa , the low-side switch is turned on for a time equal to 33% of the switching period. this reverses the inductor (primary) current, pulling current from the output filter capacitor and causing the flyback transformer to operate in for- ward mode. the low impedance presented by the trans- former secondary in forward mode dumps current into the secondary output, charging up the secondary capacitor and bringing v ina - v outa back into regula- tion. the secondary feedback loop does not improve secondary output accuracy in normal flyback mode, where the main (primary) output is heavily loaded. in this condition, secondary output accuracy is determined by the secondary rectifier drop, transformer turns ratio, and accuracy of the main output voltage. smps design procedure firmly establish the input voltage range and maximum load current before choosing a switching frequency and inductor operating point (ripple-current ratio). the primary design trade-off lies in choosing a good switch- ing frequency and inductor operating point, and the fol- lowing four factors dictate the rest of the design: input voltage range. the maximum value (v in(max) ) must accommodate the worst-case, high ac-adapter voltage. the minimum value (v in(min) ) must account for the lowest battery voltage after drops due to connectors, fuses, and battery selector switches. if there is a choice at all, lower input volt- ages result in better efficiency. maximum load current. there are two values to consider. the peak load current (i load(max) ) determines the instantaneous component stresses and filtering requirements and thus drives output capacitor selection, inductor saturation rating, and the design of the current-limit circuit. the continu- ous load current (i load ) determines the thermal stresses and thus drives the selection of input capacitors, mosfets, and other critical heat-con- tributing components. switching frequency. this choice determines the basic trade-off between size and efficiency. the opti- mal frequency is largely a function of maximum input voltage, due to mosfet switching losses that are proportional to frequency and v in 2 . the optimum fre- quency is also a moving target, due to rapid improve- ments in mosfet technology that are making higher frequencies more practical. inductor operating point. this choice provides trade-offs between size vs. efficiency and transient response vs. output ripple. low inductor values pro- vide better transient response and smaller physical size, but also result in lower efficiency and higher out- put ripple due to increased ripple currents. the mini- mum practical inductor value is one that causes the circuit to operate at the edge of critical conduction (where the inductor current just touches zero with every cycle at maximum load). inductor values lower than this grant no further size-reduction benefit. the optimum operating point is usually found between 20% and 50% ripple current. when pulse skipping ( skip low and light loads), the inductor value also determines the load-current value at which pfm/pwm switchover occurs. inductor selection the switching frequency and inductor operating point determine the inductor value as follows: for example: i load(max) = 5a, v in = 12v, v out = 5v, f osc = 300khz, 30% ripple current or lir = 0.3: find a low-loss inductor having the lowest possible dc resistance that fits in the allotted dimensions. most induc- tor manufacturers provide inductors in standard values, such as 1.0?, 1.5?, 2.2?, 3.3?, etc. also look for non-standard values, which can provide a better compro- mise in lir across the input voltage range. if using a swinging inductor (where the no-load inductance decreases linearly with increasing current), evaluate the lir with properly scaled inductance values. for the selected inductance value, the actual peak-to-peak inductor ripple current ( i inductor ) is defined by: i vvv vf l inductor out in out in osc = ? () l vx v v v x khz x a x h = ? () = 5125 12 300 5 0 3 650 . . l vvv v f i lir out in out in osc load max = ? () ()
max17003/max17004 high-efficiency, quad-output, main power- supply controllers for notebook computers 26 ______________________________________________________________________________________ ferrite cores are often the best choice, although pow- dered iron is inexpensive and can work well at 200khz. the core must be large enough not to saturate at the peak inductor current (i peak ): transformer design (for max17003/max17004 auxiliary output) a coupled inductor or transformer can be substituted for the inductor in the 5v smps to create an auxiliary output (figure 1). the max17003/max17004 is particu- larly well suited for such applications because the sec- ondary feedback threshold automatically triggers dl5 even if the 5v output is lightly loaded. the power requirements of the auxiliary supply must be considered in the design of the main output. the trans- former must be designed to deliver the required current in both the primary and the secondary outputs with the proper turns ratio and inductance. the power ratings of the synchronous-rectifier mosfets and the current limit in the max17003/max17004 m ust also be adjusted accordingly. extremes of low input-output differentials, widely different output loading levels, and high turns ratios can further complicate the design due to parasitic transformer parameters such as interwinding capaci- tance, secondary resistance, and leakage inductance. power from the main and secondary outputs is com- bined to get an equivalent current referred to the main output. use this total current to determine the current limit (see the setting the current limit section): i total = p total /v out5 where i total is the equivalent output current referred to the main output, and p total is the sum of the output power from both the main output and the secondary output: where n is the transformer turns ratio, v sec is the mini- mum required rectified secondary voltage, v fwd is the forward drop across the secondary rectifier, v out5(min) is the minimum value of the main output voltage, and v rect is the on-state voltage drop across the synchro- nous-rectifier mosfet. the transformer secondary return is often connected to the main output voltage instead of ground in order to reduce the necessary turns ratio. in this case, subtract v out5 from the secondary voltage (v sec - v out5 ) in the transformer turns-ratio equation above. the secondary diode in coupled-induc- tor applications must withstand flyback voltages greater than 60v. common silicon rectifiers, such as the 1n4001, are also prohibited because they are too slow. fast sili- con rectifiers such as the murs120 are the only choice. the flyback voltage across the rectifier is related to the v in - v out5 difference, according to the transformer turns ratio: v flyback = v sec + (v in ?v out5 ) x n where n is the transformer turns ratio (secondary wind- ings/primary windings), and v sec is the maximum sec- ondary dc output voltage. if the secondary winding is returned to v out5 instead of ground, subtract v out5 from v flyback in the equation above. the diode? reverse breakdown voltage rating must also accommo- date any ringing due to leakage inductance. the diode? current rating should be at least twice the dc load current on the secondary output. transient response the inductor ripple current also impacts transient- response performance, especially at low v in - v out dif- ferentials. low inductor values allow the inductor current to slew faster, replenishing charge removed from the output filter capacitors by a sudden load step. the total output voltage sag is the sum of the voltage sag while the inductor is ramping up, and the voltage sag before the next pulse can occur: where d max is maximum duty factor (see the electrical characteristics ), t is the switching period (1/f osc ), and t equals v out /v in x t when in pwm mode, or l x 0.2 x i max /(v in - v out ) when in skip mode. the amount of overshoot during a full-load to no-load transient due to stored inductor energy can be calculated as: v il cv soar load max out out () () 2 2 v li cvxd v itt c sag load max out in max out load max out = () ? () + ? () ? () () 2 2 n vv vvv sec fwd out rect sense = + ++ 5 ii i peak load max inductor =+ () 2
max17003/max17004 high-efficiency, quad-output, main power- supply controllers for notebook computers ______________________________________________________________________________________ 27 a) output series resistor sensing dh_ input (v in ) dl_ lx_ pgnd c in n h n l d l csh_ csl_ l b) lossless inductor sensing dh_ dl_ lx_ pgnd csh_ csl_ inductor lr dcr sense resistor l esl r sense c out r1 c eq r2 l sense r sense c eq r1 = max17003 max17004 input (v in ) c in n h n l d l c out r1 c eq max17003 max17004 r cs =r dcr r2 r1 + r2 ( ) r dcr = l c eq 1 r1 1 r2 + [ ] figure 7. current-sense configurations
max17003/max17004 high-efficiency, quad-output, main power- supply controllers for notebook computers 28 ______________________________________________________________________________________ setting the current limit the minimum current-limit threshold must be great enough to support the maximum load current when the current limit is at the minimum tolerance value. the peak inductor current occurs at i load(max) plus half the ripple current; therefore: where i limit_ equals the minimum current-limit thresh- old voltage divided by the current-sense resistance (r sense_ ). for the default setting, the minimum current- limit threshold is 45mv. connect ilim to ldo5 for a default 50mv current-limit threshold. in adjustable mode, the current-limit thresh- old is precisely 1/10th the voltage seen at ilim. for an adjustable threshold, connect a resistive divider from ref to analog ground (gnd) with ilim connected to the center tap. the external 0.5v to 2v adjustment range corresponds to a 50mv to 200mv current-limit threshold. when adjusting the current limit, use 1% tol- erance resistors and a divider current of approximately 10ma to prevent significant inaccuracy in the current- limit tolerance. the current-sense method (figure 7) and magnitude determines the achievable current-limit accuracy and power loss. typically, higher current-sense limits pro- vide tighter accuracy, but also dissipate more power. most applications employ a current-limit threshold (v limit ) of 50mv to 100mv, so the sense resistor may be determined by: for the best current-sense accuracy and overcurrent protection, use a 1% tolerance current-sense resistor between the inductor and output as shown in figure 7a. this configuration constantly monitors the inductor current, allowing accurate current-limit protection. however, the parasitic inductance of the current-sense resistor can cause current-limit inaccuracies, especially when using low-value inductors and current-sense resistors. this parasitic inductance (l esl ) can be can- celed by adding an rc circuit across the sense resistor with an equivalent time constant: alternatively, high-power applications that do not require highly accurate current-limit protection may reduce the overall power dissipation by connecting a series rc circuit across the inductor (figure 7b) with an equivalent time constant: and: where r cs is the required current-sense resistance, and r dcr is the inductor? series dc resistance. use the typical inductance and r dcr values provided by the inductor manufacturer. output capacitor selection the output filter capacitor must have low enough equiva- lent series resistance (esr) to meet output ripple and load-transient requirements, yet have high enough esr to satisfy stability requirements. the output capacitance must be high enough to absorb the inductor energy while transitioning from full-load to no-load conditions without tripping the overvoltage fault protection. when using high capacitance, low-esr capacitors (see stability require- ments), the filter capacitor? esr dominates the output voltage ripple. so the output capacitor? size depends on the maximum esr required to meet the output voltage ripple (v ripple(p-p) ) specifications: v ripple(p-p) = r esr i load(max) lir in idle mode, the inductor current becomes discontinu- ous, with peak currents set by the idle mode current- sense threshold (v idle = 0.2v limit ). in idle mode, the no-load output ripple may be determined as follows: v vr r ripple p p idle esr sense () = r l crr dcr eq =+ ? ? ? ? ? ? 1 1 1 2 r r rr r cs dcr = + ? ? ? ? ? ? 2 12 cr l r eq esl sense 1 = r v i v xi cs limit limit ilim limit == 10 ii limit load max i inductor > + ? ? ? ? ? ? () 2
max17003/max17004 high-efficiency, quad-output, main power- supply controllers for notebook computers ______________________________________________________________________________________ 29 the actual capacitance value required relates to the physical size needed to achieve low esr, as well as to the chemistry of the capacitor technology. thus, the capacitor is usually selected by esr and voltage rating rather than by capacitance value (this is true of tanta- lums, os-cons, polymers, and other electrolytics). when using low-capacity filter capacitors, such as ceramic capacitors, size is usually determined by the capacity needed to prevent v sag and v soar from causing problems during load transients. generally, once enough capacitance is added to meet the over- shoot requirement, undershoot at the rising load edge is no longer a problem (see the v sag and v soar equa- tions in the transient response section). however, low- capacity filter capacitors typically have high esr zeros that may affect the overall stability (see the output- capacitor stability considerations section). output-capacitor stability considerations stability is determined by the value of the esr zero rel- ative to the switching frequency. the boundary of insta- bility is given by the following equation: where: for a typical 300khz application, the esr zero frequen- cy must be well below 95khz, preferably below 50khz. tantalum and os-con capacitors in widespread use at the time of publication have typical esr zero fre- quencies of 25khz. in the design example used for inductor selection, the esr needed to support 25mv p-p ripple is 25mv/1.5a = 16.7m . one 220?/4v sanyo polymer (tpe) capacitor provides 15m (max) esr. this results in a zero at 48khz, well within the bounds of stability. for low-input voltage applications where the duty cycle exceeds 50% (v out /v in 50%), the output ripple voltage should not be greater than twice the internal slope- compensation voltage: v ripple 0.02 x v out where v ripple equals i inductor x r esr . the worst- case esr limit occurs when v in = 2 x v out , so the above equation may be simplified to provide the follow- ing boundary condition: r esr 0.04 x l x f sw do not put high-value ceramic capacitors directly across the feedback sense point without taking precau- tions to ensure stability. large ceramic capacitors can have a high-esr zero frequency and cause erratic, unstable operation. however, it is easy to add enough series resistance by placing the capacitors a couple of inches downstream from the feedback sense point, which should be as close as possible to the inductor. unstable operation manifests itself in two related but distinctly different ways: short/long pulses and cycle skipping resulting in lower frequency operation. instability occurs due to noise on the output or because the esr is so low that there is not enough voltage ramp in the output voltage signal. this ?ools?the error com- parator into triggering too early or into skipping a cycle. cycle skipping is more annoying than harmful, resulting in nothing worse than increased output ripple. however, it can indicate the possible presence of loop instability due to insufficient esr. loop instability can result in oscillations at the output after line or load steps. such perturbations are usually damped, but can cause the output voltage to rise above or fall below the tolerance limits. the easiest method for checking stability is to apply a very fast zero-to-max load transient and carefully observe the output-voltage-ripple envelope for over- shoot and ringing. it may help to simultaneously moni- tor the inductor current with an ac current probe. do not allow more than three cycles of ringing after the ini- tial step-response under/overshoot. f rc esr esr out = 1 2 f f esr osc
max17003/max17004 high-efficiency, quad-output, main power- supply controllers for notebook computers 30 ______________________________________________________________________________________ input capacitor selection the input capacitor must meet the ripple current requirement (i rms ) imposed by the switching currents. for an out-of-phase regulator, the total rms current in the input capacitor is a function of the load currents, the input currents, the duty cycles, and the amount of overlap as defined in figure 8. the 40/60 optimal interleaved architecture of the max17003/max17004 allows the input voltage to go as low 8.3v before the duty cycles begin to overlap. this offers improved efficiency over a regular 180 out-of- phase architecture where the duty cycles begin to overlap below 10v. figure 8 shows the input-capacitor rms current vs. input voltage for an application that requires 5v/5a and 3.3v/5a. this shows the improve- ment of the 40/60 optimal interleaving over 50/50 inter- leaving and in-phase operation. for most applications, nontantalum chemistries (ceram- ic, aluminum, or os-con) are preferred due to their resistance to power-up surge currents typical of sys- tems with a mechanical switch or connector in series with the input. choose a capacitor that has less than 10? temperature rise at the rms input current for opti- mal reliability and lifetime. power-mosfet selection most of the following mosfet guidelines focus on the challenge of obtaining high load-current capability when using high-voltage (> 20v) ac adapters. low- current applications usually require less attention. the high-side mosfet (n h ) must be able to dissipate the resistive losses plus the switching losses at both v in(min) and v in(max) . ideally, the losses at v in(min) should be roughly equal to the losses at v in(max) , with figure 8. input rms current iiddiiddiiididdd d v v d v v d duty cycle overlap fraction i vi vi v rms out in lx ol out in lx ol out out in ol in lx lx ol lx out in lx out in ol in out out out out =? () ? () +? () ? () ++? () +? ?+ () === = + ? 5 2 53 2 353 2 2 53 5 5 3 3 55 33 1 in in rms load out in out in ii vvv v = ? () ? ? ? ? ? ? ? ? ? ? input rms current for interleaved operation: input rms current for single-phase operation: input-capacitor rms current vs. input voltage v in (v) i rms (a) 18 16 12 14 10 8 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 620 in phase 50/50 interleaving 40/60 optimal interleaving
max17003/max17004 high-efficiency, quad-output, main power- supply controllers for notebook computers ______________________________________________________________________________________ 31 lower losses in between. if the losses at v in(min) are significantly higher, consider increasing the size of n h . conversely, if the losses at v in(max) are significantly higher, consider reducing the size of n h . if v in does not vary over a wide range, maximum efficiency is achieved by selecting a high-side mosfet (n h ) that has conduc- tion losses equal to the switching losses. choose a low-side mosfet (n l ) that has the lowest pos- sible on-resistance (r ds(on) ), comes in a moderate-sized package (i.e., 8-pin so, dpak, or d 2 pak), and is reason- ably priced. ensure that the max17003/max17004 dl_ gate driver can supply sufficient current to support the gate charge and the current injected into the parasitic drain-to-gate capacitor caused by the high-side mosfet turning on; otherwise, cross-conduction problems may occur. switching losses are not an issue for the low-side mosfet since it is a zero-voltage switched device when used in the step-down topology. power-mosfet dissipation worst-case conduction losses occur at the duty-factor extremes. for the high-side mosfet (n h ), the worst- case power dissipation due to resistance occurs at mini- mum input voltage: generally, use a small high-side mosfet to reduce switching losses at high input voltages. however, the r ds(on) required to stay within package power-dissipa- tion limits often limits how small the mosfet can be. the optimum occurs when the switching losses equal the conduction (r ds(on) ) losses. high-side switching losses do not become an issue until the input is greater than approximately 15v. calculating the power dissipation in high-side mosfets (n h ) due to switching losses is difficult, since it must allow for difficult-to-quantify factors that influence the turn- on and turn-off times. these factors include the internal gate resistance, gate charge, threshold voltage, source inductance, and pc board layout characteristics. the fol- lowing switching-loss calculation provides only a very rough estimate and is no substitute for breadboard evalu- ation, preferably including verification using a thermocou- ple mounted on n h : where c oss is the output capacitance of n h , q g(sw) is the charge needed to turn on the n h mosfet, and i gate is the peak gate-drive source/sink current (1a typ). switching losses in the high-side mosfet can become a heat problem when maximum ac adapter voltages are applied, due to the squared term in the switching- loss equation (c x v in 2 x f sw ). if the high-side mosfet chosen for adequate r ds(on) at low battery voltages becomes extraordinarily hot when subjected to v in(max) , consider choosing another mosfet with lower parasitic capacitance. for the low-side mosfet (n l ), the worst-case power dissipation always occurs at maximum battery voltage: the absolute worst case for mosfet power dissipation occurs under heavy overload conditions that are greater than i load(max) but are not high enough to exceed the current limit and cause the fault latch to trip. to protect against this possibility, ?verdesign?the cir- cuit to tolerate: where i limit is the peak current allowed by the current- limit circuit, including threshold tolerance and sense- resistance variation. the mosfets must have a relatively large heatsink to handle the overload power dissipation. choose a schottky diode (d l ) with a forward-voltage drop low enough to prevent the low-side mosfet? body diode from turning on during the dead time. as a general rule, select a diode with a dc current rating equal to 1/3rd the load current. this diode is optional and can be removed if efficiency is not critical. boost capacitors the boost capacitors (c bst ) must be selected large enough to handle the gate-charging requirements of the high-side mosfets. typically, 0.1? ceramic capacitors work well for low-power applications driving medium-sized mosfets. however, high-current appli- cations driving large, high-side mosfets require boost capacitors larger than 0.1?. for these applications, select the boost capacitors to avoid discharging the capacitor more than 200mv while charging the high- side mosfets?gates: ii i load limit inductor =? ? ? ? ? ? ? 2 pd n sistive v v ir l out in max load ds on re () () () = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? () 1 2 pd n sistive iq i cv vf h load g sw gate oss in max in max sw re () ( ) () () = + ? ? ? ? ? ? 2 pd n sistive v v ir h out in load ds on re () () = ? ? ? ? ? ? () 2
max17003/max17004 high-efficiency, quad-output, main power- supply controllers for notebook computers 32 ______________________________________________________________________________________ where q gate is the total gate charge specified in the high-side mosfet? data sheet. for example, assume the fds6612a n-channel mosfet is used on the high side. according to the manufacturer? data sheet, a sin- gle fds6612a has a maximum gate charge of 13nc (v gs = 5v). using the above equation, the required boost capacitance would be: selecting the closest standard value, this example requires a 0.1? ceramic capacitor. ldoa design procedure output voltage selection adjust the auxiliary linear regulator? output voltage by connecting a resistive divider between outa and ana- log ground with the center tap connected to fba (figure 1). select r6 in the 10k to 30k range, and calculate r5 with the following equation: where v fba = 1.0v. transistor selection the pass transistor must meet specifications for current gain ( ), input capacitance, collector-emitter saturation voltage, and power dissipation. the transistor? current gain limits the guaranteed maximum output current to: where i drv is the minimum guaranteed base drive cur- rent, v be is the base-to-emitter voltage of the transistor, and r be is the pullup resistor connected between the transistor? base and emitter. furthermore, the transis- tor? current gain increases the linear regulator? dc loop gain (see the ldoa stability requirements sec- tion), so excessive gain destabilizes the output. therefore, transistors with current gain over 100 at the maximum output current can be difficult to stabilize and are not recommended. the transistor? input capaci- tance and input resistance also create a second pole, which could be low enough to make the output unsta- ble when heavily loaded. the transistor? saturation voltage at the maximum out- put current determines the minimum input-to-output voltage differential that the linear regulator supports. alternatively, the package? power dissipation could limit the useable maximum input-to-output voltage dif- ferential. the maximum power-dissipation capability of the transistor? package and mounting must exceed the actual power dissipation in the device. the power dissi- pation equals the maximum load current times the max- imum input-to-output differential: pwr = i load(max) (v ina - v outa ) pwr = i load(max) v ce ldoa stability requirements the m ax17003/max17004 linear-regulator controller uses an internal transconductance amplifier to drive an external pnp pass transistor. the transconductance amplifier, the pass transistor, the base-to-emitter resistor, and the output capacitor determine the loop stability. the transconductance amplifier regulates the output voltage by controlling the pass transistor? base cur- rent. the total dc loop gain is approximately: where v t is 26mv at room temperature, h fe is the pass transistor? dc gain, and i bias is the current through the base-to-emitter resistor (r be ). the 680 base-to- emitter resistor used in figure 1 was chosen to provide a 1ma bias current (i bias ). a v v ih i v ldo t bias fe load () . = ? ? ? ? ? ? + ? ? ? ? ? ? 55 1 ii load max drv v r min be be () = ? ? ? ? ? ? ? rr v v outa fba 56 1 =? ? ? ? ? ? ? c nc mv f bst == 13 200 0 065 . c q mv bst gate = 200
max17003/max17004 high-efficiency, quad-output, main power- supply controllers for notebook computers ______________________________________________________________________________________ 33 the output capacitor and the load resistance create the dominant pole in the system. however, the internal ampli- fier delay, the pass transistor? input capacitance, and the stray capacitance at the feedback node create additional poles in the system, and the output capacitor? esr gen- erates a zero. for proper operation, use the following steps to ensure the linear-regulator stability: 1) first, calculate the dominant pole set by the linear regulator? output capacitor and the load resistor: where c outa is the output capacitance of the aux- iliary ldo and r load is the load resistance corre- sponding to the maximum load current. the unity- gain crossover of the linear regulator is: f crossover = a v(ldo) f pole(ldo) 2) the pole caused by the internal amplifier delay is at approximately 1mhz: f pole(amp) 1mhz 3) next, calculate the pole set by the transistor? input capacitance, the transistor? input resistance, and the base-to-emitter pullup resistor. since the transistor? input resistance (h fe /g m ) is typically much greater than the base-to-emitter pullup resistance, the pole can be determined from the simplified equation: where g m is the transconductance of the pass tran- sistor, and f t is the transition frequency. both para- meters can be found in the transistor? data sheet. therefore, the equation can be further reduced to: 4) next, calculate the pole set by the linear regulator? feedback resistance and the capacitance between fba and ground (approximately 5pf including stray capacitance): 5) next, calculate the zero caused by the output capacitor? esr: where r esr is the equivalent series resistance of c outa . 6) to ensure stability, choose c outa large enough so that the crossover occurs well before the poles and zero calculated in steps 2 through 5. the poles in steps 3 and 4 generally occur at several mhz, and using ceramic output capacitors ensures the esr zero occurs at several mhz as well. placing the crossover frequency below 500khz is typically suf- ficient to avoid the amplifier delay pole and gener- ally works well, unless unusual component selection or extra capacitance moves the other poles or zero below 1mhz. a capacitor connected between the linear regula- tor? output and the feedback node can improve the transient response and reduce the noise cou- pled into the feedback loop. if a low-dropout solution is required, an external p- channel mosfet pass transistor could be used. however, a pmos-based linear regulator requires higher output capacitance to stabilize the loop. the high gate capacitance of the p-channel mosfet lowers the f pole(cin) and can cause instability. a large output capacitance must be used to reduce the unity-gain bandwidth and ensure that the pole is well above the unity-gain crossover frequency. applications information duty-cycle limits minimum input voltage the minimum input operating voltage (dropout voltage) is restricted by the maximum duty-cycle specification (see the electrical characteristics table). keep in mind that the transient performance gets worse as the step- down regulators approach the dropout voltage, so bulk output capacitance must be added (see the voltage sag and soar equations in the transient response section of the smps design procedure section). the absolute point of dropout occurs when the inductor current ramps down during the off-time ( i down ) as much as it ramps up during the on-time ( i up ). this results in a minimum operating voltage defined by the following equation: f cr zero esr outa esr () = 1 2 f crr pole fba fba () (||) = 1 256 f f h pole cin t fe () f cr c g f pole cin in in in m t () = 1 2 2 f cr pole ldo outa load () = 1 2
max17003/max17004 high-efficiency, quad-output, main power- supply controllers for notebook computers 34 ______________________________________________________________________________________ where v chg and v dis are the parasitic voltage drops in the charge and discharge paths, respectively. a rea- sonable minimum value for h is 1.5, while the absolute minimum input voltage is calculated with h = 1. maximum input voltage the max17003/max17004 controllers include a mini- mum on-time specification, which determines the maxi- mum input operating voltage that maintains the selected switching frequency (see the electrical characteristics table). operation above this maximum input voltage results in pulse-skipping operation, regardless of the operating mode selected by skip . at the beginning of each cycle, if the output voltage is still above the feedback threshold voltage, the controller does not trigger an on-time pulse, effectively skipping a cycle. this allows the controller to maintain regulation above the maximum input voltage, but forces the con- troller to effectively operate with a lower switching fre- quency. this results in an input threshold voltage at which the controller begins to skip pulses (v in(skip) ): where f osc is the switching frequency selected by fsel. pcb layout guidelines careful pcb layout is critical to achieving low switching losses and clean, stable operation. the switching power stage requires particular attention (figure 9). if possible, mount all the power components on the top side of the board, with their ground terminals flush against one another. follow these guidelines for good pcb layout: keep the high-current paths short, especially at the ground terminals. this practice is essential for sta- ble, jitter-free operation. keep the power traces and load connections short. this practice is essential for high efficiency. using thick copper pcbs (2oz vs. 1oz) can enhance full- load efficiency by 1% or more. correctly routing pcb traces is a difficult task that must be approached in terms of fractions of centimeters, where a single milliohm of excess trace resistance causes a measurable efficiency penalty. minimize current-sensing errors by connecting csh_ and csl_ directly across the current-sense resistor (r sense_ ). when trade-offs in trace lengths must be made, it is preferable to allow the inductor charging path to be made longer than the discharge path. for example, it is better to allow some extra distance between the input capacitors and the high-side mosfet than to allow distance between the inductor and the low- side mosfet or between the inductor and the out- put filter capacitor. route high-speed switching nodes (bst_, lx_, dh_, and dl_) away from sensitive analog areas (ref, fb_, csh_, csl_). layout procedure place the power components first, with ground termi- nals adjacent (n l _ source, c in , c out _, and d l _ anode). if possible, make all these connections on the top layer with wide, copper-filled areas. mount the controller ic adjacent to the low-side mosfet, preferably on the back side opposite n l_ and n h_ in order to keep lx_, gnd, dh_, and the dl_ gate-drive lines short and wide. the dl_ and dh_ gate traces must be short and wide (50 mils to 100 mils wide if the mosfet is 1in from the controller ic) to keep the driver impedance low and for proper adaptive dead-time sensing. group the gate-drive components (bst_ capacitor, ldo5 bypass capacitor) together near the controller ic. make the dc-dc controller ground connections as shown in figures 1 and 9. this diagram can be viewed as having two separate ground planes: power ground, where all the high-power components go, and an ana- log ground plane for sensitive analog components. the analog ground plane and power ground plane must meet only at a single point directly at the ic. connect the output power planes directly to the output filter capacitor positive and negative terminals with mul- tiple vias. place the entire dc-dc converter circuit as close to the load as is practical. vv ft in skip out osc on min () () = ? ? ? ? ? ? 1 vvvh d vv in min out chg max out dis () =+ + ? ? ? ? ? ? ? + () 1 1
max17003/max17004 high-efficiency, quad-output, main power- supply controllers for notebook computers ______________________________________________________________________________________ 35 via to power ground max17003/max17004 ref bypass capacitor connect gnd and pgnd to the controller at one point only as shown connect the exposed pad to analog gnd inductor c out c out input kelvin sense vias under the sense resistor (refer to the evaluation kit) ground output inductor c out c in input ground output dh lx dl high-power layout low-power layout dual n-channel mosfet single n-channel mosfets c in figure 9. pcb layout chip information transistor count: 6897 process: bicmos feature max8744/max8745 max17003/max17004 startup s tar tup op er ati ng m od e d ep end s on the skip setti ng . ( e.g ., skip i s l ow , then star tup occur s i n ski p m od e) . startup is always in low-noise pulse-skipping mode (i.e., same as skip = ref setting). this allows for startup into prebiased outputs. the skip setting takes effect once the smps is in regulation. shutdown actively discharges the output down to zero. soft discharge of the output using the dschg3 and dschg5 pins. dl3 and dl5 states dl3 and dl5 are high in shutdown. dl3 and dl5 are latched high during an ov fault of the respective output (max8744 only). dl3 and dl5 are low in shutdown. dl3 and dl5 are latched high during an ov fault of the respective output (max17003 only). power-good pgood3: power-good indicator for smps3. pgood5: power-good indicator for smps5. p go od a: p ow er - g ood i nd i cator for the auxi l i ar y ld o. pgdall: power-good indicator for smps3 and smps5. auxiliary ldo does not have power-good indicator. t t a a b b l l e e 6 6 . . f f u u n n c c t t i i o o n n a a l l d d i i f f f f e e r r e e n n c c e e s s b b e e t t w w e e e e n n m m a a x x 8 8 7 7 4 4 4 4 / / m m a a x x 8 8 7 7 4 4 5 5 a a n n d d m m a a x x 1 1 7 7 0 0 0 0 3 3 / / m m a a x x 1 1 7 7 0 0 0 0 4 4
max17003/max17004 high-efficiency, quad-output, main power- supply controllers for notebook computers maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 36 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2007 maxim integrated products is a registered trademark of maxim integrated products, inc. qfn thin.eps package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .)

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